WV3DG72256V-AD2 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary 2gb C 2x128mx72 sdram, registered features burst mode operation auto and self refresh capability lvttl compatible inputs and outputs serial presence detect with eeprom fully synchronous: all signals are registered on the positive edge of the system clock programmable burst lengths: 1, 2, 4, 8 or full page 3.3v 0.3v power supply dual rank 168 pin dimm jedec ? pcb - ad2: 28.58mm (1.125) typ description the wv3dg72256v is a 2x128mx72 synchronous dram module which consists of eighteen 256mx4 stack sdram com po nents (stacked from 128mx4) in tsop ii package, two 18 bit drive ics for input control signal and one 2kb eeprom in an 8 pin tssop package for serial presence detect which are mounted on a 168 pin dimm mul ti lay er fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option pin names a0 C a12 address input (multiplexed) ba0-1 select bank dq0-63 data input/output cb0-7 check bit (data-in/data-out) clk0 clock input cke0 clock enable input cs0# - cs3# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-7 dqm v cc power supply (3.3v) v ss ground v ref power supply for reference rege register enable sda serial data i/o scl serial clock sa0-2 address in eeprom nc no connect * pins not used in this module. pin configurations (front side/back side) pin front pin back pin front pin back pin back pin back 1v ss 29 dqm1 57 dq18 85 v ss 113 dqm5 141 dq50 2 dq0 30 cs0# 58 dq19 86 dq32 114 cs1# 142 dq51 3 dq1 31 nc 59 v cc 87 dq33 115 ras# 143 v cc 4 dq2 32 v ss 60 dq20 88 dq34 116 v ss 144 dq52 5 dq3 33 a0 61 nc 89 dq35 117 a1 145 nc 6v cc 34 a2 62 *vref 90 v cc 118 a3 146 *v ref 7 dq4 35 a4 63 *cke1 91 dq36 119 a5 147 rege 8 dq5 36 a6 64 v ss 92 dq37 120 a7 148 v ss 9 dq6 37 a8 65 dq21 93 dq38 121 a9 149 dq53 10 dq7 38 a10/ap 66 dq22 94 dq39 122 ba0 150 dq54 11 dq8 39 ba1 67 dq23 95 dq40 123 a11 151 dq55 12 v ss 40 v cc 68 v ss 96 v ss 124 v cc 152 v ss 13 dq9 41 v cc 69 dq24 97 dq41 125 nc 153 dq56 14 dq10 42 clk0 70 dq25 98 dq42 126 a12 154 dq57 15 dq11 43 v ss 71 dq26 99 dq43 127 v ss 155 dq58 16 dq12 44 nc 72 dq27 100 dq44 128 cke0 156 dq59 17 dq13 45 cs2# 73 v cc 101 dq45 129 cs3# 157 v cc 18 v cc 46 dqm2 74 dq28 102 v cc 130 dqm6 158 dq60 19 dq14 47 dqm3 75 dq29 103 dq46 131 dqm7 159 dq61 20 dq15 48 nc 76 dq30 104 dq47 132 nc 160 dq62 21 cb0 49 v cc 77 dq31 105 cb4 133 v cc 161 dq63 22 cb1 50 nc 78 v ss 106 cb5 134 nc 162 v ss 23 v ss 51 nc 79 nc 107 v ss 135 nc 163 nc 24 nc 52 cb2 80 nc 108 nc 136 cb6 164 nc 25 nc 53 cb3 81 wp 109 nc 137 cb7 165 sa0 26 v cc 54 v ss 82 sda 110 v cc 138 v ss 166 sa1 27 we# 55 dq16 83 scl 111 cas# 139 dq48 167 sa2 28 dqm0 56 dq17 84 v cc 112 dqm4 140 dq49 168 v cc
WV3DG72256V-AD2 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary* functional block diagram bcs1#, b 2 cke0 bcs0#, b 0 cke0 b 0 a0~b 0 a12 bdqm0 bcs2, b 1 cke0 a 3 ~a1 0, ba0 b 0 a 3 ~b 0 a 10 , b 0 ba0 b 1 a 3 ~b 1 a 10 , b 1 ba0 b 0 a 11 , b 0 a 12 , b 0 ba1 b 0 cke0, b 1 cke0 b 2 cke0,b 3 cke0 b 1 a 11 , b 1 a 12 , b 1 ba1 bcs2, bcs3 b 0 a 0 , b 0 a 1, b 0 ba 2 b 1 a 0 , b 1 a 1 ,b 1 ba 2 b 0 ras#, bcas#, b 0 we# b 1 ras#, bcas#, b 1 we# bcs0, bcs1 bcs3#, b 3 cke0 pclk5 dq0~3 pclk1 pclk2 pclk3 pclk4 dq0~7 dq0~11 dq0~15 cb0~3 10 dq32~35 dq36~39 dq40~43 dq44~47 dq4~7 bdqm4 bdqm5 10 10 10 10 10 10 10 10 pclk6 dq16~19 10 pclk7 dq20~23 10 pclk8 pclk9 rege cke0 cs2#, cs3# cs0#, cs1# dqm0, 1, 4, 5 dqm0, 1, 4, 5 ras#, cas#, we# a 11 , a 12 , ba 1 a 0, a 1 , a 2 dqm2, 3, 6, 7 dqm2, 3, 6, 7 dq24~27 10 dq28~31 10k v cc dq60~63 10 10 12pf clk1,2,3 10 12pf clk0,2,3 v ss v cc dq56~59 10 dq52~55 10 dq48~51 10 10 pclk0 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 b 0 ras#, b 0 cas#, b 0 we#, b 0 ba0, b 0 ba1 b 1 a0~b 1 a12 b 1 ras#, b 1 cas#, b 1 we#, b 1 ba0, b 1 ba1 g agnd av cc iy0 iy1 iy2 iy3 iy4 iy5 iy6 iy7 iy8 iy9 *1 clk cb note 1. the actual values of cb will depend upon the pll chosen. fbin fbout cdcf2510 pclk0 pclk1 pclk2 pclk3 pclk4 pclk5 pclk6 pclk7 pclk8 pclk9 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 clk# cs0, cke ctl add dqm dq0~3 clk# cs1, cke ctl add dqm dq0~3 bdqm6 bdqm2 bdqm3 le oe# le oe# le oe# 74alvcf162835 74alvcf162835 74alvcf162835 scl 47k sda sa0 sa1 sa2 serial pd wp a0 a1 a2
WV3DG72256V-AD2 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 36 w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. recommended dc operating conditions voltage referenced to: v ss = 0v, 0c t a 70 parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v ccq +0.3 v 1 input low voltage v il -0.3 0.8 v 2 output high voltage v oh 2.4 v i oh = -2ma output low voltage v ol 0.4 v i ol = -2ma input leakage current i li -10 10 a 3 note: 1. v ih (max)= 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min)= -2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v ccq input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. capacitance t a = 25 c, f = 1mhz, v cc = 3.3v, v ref = 1.4v 200mv parameter symbol max unit input capacitance (a0-a12, ba0-ba1) c in1 15 pf input capacitance (ras#, cas#, we#) c in2 15 pf input capacitance (cke0) c in3 15 pf input capacitance (clk0) c in4 20 pf input capacitance (cs0# - cs3#) c in5 15 pf input capacitance (dqm0-dqm7) c in6 15 pf data input/output capacitance (dq0-dq63), (cb0-bc7) c out 22 pf preliminary*
WV3DG72256V-AD2 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary* operating current characteristics v cc = 3.3v, 0c t a 70c notes: 1. measured with outputs open. 2. refresh period is 64ms. parameters symbol conditions versions units note 133/100 operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i ol = 0ma 2,520 ma 1 precharge standby current in power down mode i cc2p c ke v il (max), t cc = 10ns 530 ma i cc2ps c ke & clk v il (max), t cc = 130 ma precharge standby current in non-power down mode i cc2n c ke v ih (min), cs v ih (min), t cc =10ns input signals are charged one time during 20 1,170 ma i cc2ns c ke v ih (min), clk v il (max), t cc = input signals are stable 410 ma active standby current in power-down mode i cc3p c ke v il (max), t cc = 10ns 670 ma i cc3ps c ke & clk v il (max), t cc = 270 ma active standby in current non power- down mode i cc3n c ke v ih (min), cs v ih (min), t cc = 10ns input signals are charged one time during 20ns 1,530 ma i cc3ns c ke v ih (min), clk v il (max), t cc = input signals are stable 950 ma operating current (burst mode) i cc4 io = ma page burst 4 banks activated t ccd = 2clk 2,610 ma 1 refresh current i cc5 t rc t rc (min) 4,590 ma 2 self refresh current i cc6 c ke 0.2v 420 ma
WV3DG72256V-AD2 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 ac operating test conditions v cc = 3.3v, 0c t a 70c parameter value units ac input level (v in /v il ) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2 ac operating test conditions parameter symbol value units notes 133/100 row active to row active delay t rrd(min) 15 ns 1 ras# to cas# delay t rcd(min) 20 ns 1 row precharge time t rp(min) 20 ns 1 row active time t ras(min) 45 ns 1 t ras(max) 100 s row cycle time t rc(min) 65 ns 1 last data in to row precharge t rdl(min) 2 clk 2 last data in to active delay t dal(min) 2 clk + t rp last data in to new col. address delay t cdl(min) 1 clk 1 last data in to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1 clk 2 number of valid output data cas latency = 3 2 clk 3 cas latency = 2 1 ea 4 notes: 1. the minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and the n rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. 3.3v 1220 870 output v oh (dc)=2.4v, i oh =-2ma v ol (dc)=2.4v, i ol =-2ma (fig. 1) dc output load circuit (fig. 2) ac output load circuit 50pf v tt =1.4v 50 output 50pf z0 = 50 preliminary*
WV3DG72256V-AD2 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 operating ac parameter parameter symbol 133/100 units notes min max clk cycle time cas latency = 3 t cc 7.5 1,000 ns 1 cas latency = 2 C clk to valid output delay cas latency = 3 t sac 5.4 ns 1, 2 cas latency = 2 C output data hold time cas latency = 3 t oh 3 ns 2 cas latency = 2 C clk high pulse width t ch 2.5 ns 3 clk low pulse width t cl 2.5 ns 3 input setup time t ss 1.5 ns 3 input hold time t sh 0.8 ns 3 clk to output in low-z t slz 1ns2 clk to output in hi-z cas latency = 3 t hz 5.4 ns cas latency = 2 C notes: 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr &tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter. preliminary*
WV3DG72256V-AD2 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary* * all dimensions are in millimeters and (inches) package dimensions for ad2 133.350 5.250 127.350 5.014 8.86 max (0.270 max) 1.2700.10 0.0500.0039 2.000 0.079 0.157 0.004 (4.000 0.100) 6.350 0.250 36.830 1.450 54.64 2.150 3.000 0.118 3.00 0.118 8.890 0.350 17.780 0.700 2.540 min 0.100 min 0.165 min 4.19 min 118dia 0.004 3.000dia 0.100 ? 6.350 0.250 11.430 (0.450) 115.57 4.550 1.372 0.054 28.575 typ 1.125 ordering information for ad2 part number clock speed cas latency height* wv3dg72256v10ad2xx 100mhz cl=2 28.58 (1.25) typ wv3dg72256v7ad2xx 133mhz cl=2 28.58 (1.25) typ wv3dg72256v75ad2xx 133mhz cl=3 28.58 (1.25) typ notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult f actory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
WV3DG72256V-AD2 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary* part numbering guide wv 3 d g 72 256 v xx ad2 i- x g wedc memory sdram gold bus width depth 3.3 volts clock speed (mhz) 10 = 100mhz @ cl = 2 7 = 133mhz @ cl = 2 75 = 133mhz @ cl = 3 package 168 pin dimm ad2: 28.58mm (1.125) industrial temp component vendor name (m = micron) (s = samsung) g = rohs compliant
WV3DG72256V-AD2 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs january 2006 rev. 0 preliminary* document title 2gb- 2x128mx72 sdram, registered revision history rev # history release date status rev 0 created data sheet january 2006 advanced
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